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This edition first published 2016
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Contents

About the Authors

Acknowledgements

Preface

1 Introduction

1.1 A Brief Timeline of Consumer Electronics
1.2 The Electromagnetic Spectrum
1.3 Industry Trends
1.4 Forms of Wireless Communication
1.5 Conclusion
References

2 Transmitters and Receivers

2.1 Introduction
2.2 Transmitter and Receiver Components
2.3 Noise and Interference
2.4 Introduction to Modulation
2.5 Digital Modulation
2.6 Noise Analysis and Link Budget Calculation
2.7 Some Wireless Transceiver Architectures
2.8 Conclusion
References

3 Scattering Parameters

3.1 Introduction
3.2 Z-Parameters (Open-Circuit Impedance Parameters)
3.3 Y-Parameters (Short-Circuit Admittance Parameters)
3.4 H-Parameters (Hybrid Parameters)
3.5 ABCD-Parameters (Transmission or Chain Parameters)
3.6 Summary of Two-Port Parameter Operations
3.7 Scattering Parameters
3.8 Transmission Parameters
References

4 Lumped-Element Filters

4.1 Introduction
4.2 Filter Theory
4.3 Butterworth, Chebyshev and Elliptic Low-Pass Prototypes
4.4 Filter Design Method
4.5 Practical Lumped Elements
4.6 Capacitively-Coupled Resonator Filter
References

5 Transmission Line Theory

5.1 Introduction
5.2 Reflections on Transmission Lines
5.3 Transmission Line Theory
5.4 Standing Waves on a Lossless Transmission Line with Mismatched Load
5.5 The Smith Chart
5.6 The Signal Flow Graph
5.7 Conclusion
References

6 Transmission Line Components

6.1 Introduction
6.2 Coaxial Components
6.3 Twisted Pairs and Twin-Lead
6.4 Rectangular Waveguide
6.5 Microstrip
6.6 Common Microstrip Components
6.7 Uniplanar Transmission Lines
6.8 Other Transmission Line Types
6.9 Conclusion
References

7 Transmission Line Filters

7.1 Introduction
7.2 Unloaded Q of a Transmission Line Resonator
7.3 Lumped-to-Distributed Conversion
7.4 Impedance and Admittance Inverters
7.5 Richards Transformation
7.6 Unit Element, Kuroda's Identity and Coupled-Lines Section
7.7 Stepped-Impedance Low-Pass Filter
7.8 Parallel-Coupled Line Filter
7.9 Interdigital Filter
7.10 Combline Filter
7.11 Hairpin Filter
7.12 Cross-Coupled Filters
7.13 Conclusion
References

8 Semiconductor Devices

8.1 Introduction
8.2 Fabrication Technology
8.3 Field-Effect Transistors
8.4 Bipolar Transistors
8.5 Package Styles
8.6 High-Power Transistors
8.7 RFICs and MMICs
8.8 Two-Terminal Devices
References

9 Impedance Matching

9.1 Introduction
9.2 The Purpose of Impedance Matching
9.3 Lumped-Element Matching Networks
9.4 Distributed Matching Networks
9.5 The Cyclic Nature of Distributed Circuits
9.6 Conclusion
References

10 Amplifiers

10.1 Introduction
10.2 Transistor Configurations
10.3 Classical Analysis of Gain and Stability
10.4 DC Biasing
10.5 Common Amplifier Topologies
10.6 Low-Noise Amplifiers
10.7 Nonlinearity and Intermodulation
10.8 Power Amplifier Classes of Operation
10.9 Power-Combining Techniques
10.10 Power Amplifier Linearisation
10.11 Conclusion
References

11 Oscillators

11.1 Introduction
11.2 Basic Concepts
11.3 Resonators
11.4 Some Oscillator Circuits
11.5 Oscillator Design Procedure
11.6 Conclusion
References

12 Mixers and Modulators

12.1 Introduction
12.2 Single-Ended Mixers
12.3 Balanced and Image-Rejection Mixers
12.4 Baluns and Couplers
12.5 Common Mixer Circuits
12.6 Modulators
12.7 Mixer Linearisation and Adaptive Signal Cancellation
12.8 Conclusion
References

13 RF MEMS

13.1 Introduction
13.2 Novel Transceiver Architectures using RF MEMS
13.3 Micromachined Transmission Lines and Passive Elements
13.4 RF MEMS Switches
13.5 Reconfigurable Impedance-Matching Networks
13.6 MEMS Phase Shifters
13.7 Tuneable Filters
13.8 MEMS Antennas
13.9 RF MEMS Fabrication and Packaging
13.10 Reliability and Design Consideration of RF MEMS Devices
References

14 Antennas and Propagation

14.1 Introduction
14.2 Antenna Systems
14.3 Transmission Equations, Free-Space Path Loss and Link Budget Calculation
14.4 Other Propagation Effects
14.5 Millimetre-Wave and THz Propagation
14.6 Indoor Propagation
14.7 Outdoor Propagation
14.8 Multipath Propagation
14.9 Antenna Arrays
14.10 Multiple-Input and Multiple-Output Systems
References

15 Digital Signal Processing for Transceivers

15.1 Introduction
15.2 RF Performance Challenges
15.3 DSP in Modern Wireless Communications Systems
15.4 Signal Conversion and Processing
15.5 Digital Calibration for I–Q Imbalance
15.6 Digital Predistortion Techniques
15.7 DSP Techniques for OFDM
15.8 MIMO
15.9 Conclusion
References

16 Packaging and Assembly

16.1 Introduction
16.2 Technology Options and System Partitioning
16.3 PCB/Laminate Technology
16.4 Thin-Film Fabrication
16.5 Thick-Film Fabrication
16.6 LTCC Technology
16.7 Chip Packaging
16.8 Manufacturing using Surface Mount Technology
16.9 System-in-Package and System-on-Substrate Technology
16.10 Transitions and Antenna-in-Package Techniques
16.11 Conclusion
References

17 Electronic Design Automation

17.1 Introduction
17.2 Linear Frequency-Domain Analysis
17.3 Time-Domain Simulation
17.4 Harmonic Balance
17.5 Large-Signal/Small-Signal Simulation
17.6 Planar Electromagnetic Simulation
17.7 3-D Electromagnetic Simulation
17.8 Integrated Circuit Simulation and Layout
17.9 Conclusion
References

18 Measurement Techniques

18.1 Introduction
18.2 The Oscilloscope
18.3 Function Generator and Arbitrary Waveform Generator
18.4 LCR Meters and Component Analysers
18.5 Signal Generators
18.6 Spectrum and Signal Analysers
18.7 Vector Network Analysers
18.8 Microstrip Test Fixture Measurements
18.9 Probe Station Measurements
18.10 Mixed-Mode S-Parameters
18.11 Source- and Load-Pull Measurements
18.12 X-Parameter Measurements
References

Glossary

Index

EULA

List of Illustrations

Chapter 1

Figure 1.1 Microprocessor transistor count versus year on a linear scale.
Figure 1.2 A simplified timeline of developments in consumer electronics.
Figure 1.3 Frequency, wavelength and terminology for various applications of electromagnetic waves.
Figure 1.4 (a) Idealised point source transmitter giving omnidirectional coverage. (b) Doughnut-shaped radiation pattern from a typical terrestrial transmitter. (c) Pencil beam from a satellite dish.
Figure 1.5 Trend of atmospheric attenuation at sea level; see Ref. [4] for data.
Figure 1.6 Various wireless communications standards compared.
Figure 1.7 Aspects of modern RF engineering.
Figure 1.8 The UK's main terrestrial TV transmitter sites.
Figure 1.9 Illustration of multipath propagation and its limiting effect on symbol rate.
Figure 1.10 The OFDM principle; the data is spread out over many sub-carriers to lower the symbol rate in each.
Figure 1.11 (a) TV broadcast satellite in geostationary orbit. The elevation from London is shown. (b) An example LEO satellite constellation.
Figure 1.12 Satellite dish beam-width; low- and high-gain antennas compared.
Figure 1.13 Components of a satellite TV installation.
Figure 1.14 Satellite HD TV STB block diagram.
Figure 1.15 A cellular system.
Figure 1.16 A simplified block diagram of a mobile phone.
Figure 1.17 Rako® wireless control products using the 433 MHz band. Left: Controls and app. Right: A motorised curtain/blind unit. Images © 2016 Rako Controls Ltd., used with permission.
Figure 1.18 A simplified representation of RFID using backscatter modulation.
Figure 1.19 A passive RFID tag block diagram.
Figure 1.20 Instrumentel™ wireless telemetry system for gas turbine diagnostics. Illustration © Instrumentel Ltd. Used with permission; all rights reserved.

Chapter 2

Figure 2.1 Simplified block diagram of a transmitter and receiver for wireless communication.
Figure 2.2 Output spectrum of (a) an ideal oscillator, and (b) a practical oscillator.
Figure 2.3 Mixer. (a) Symbol and function. (b) Simplified spectrum.
Figure 2.4 Band-pass filter function.
Figure 2.5 Basic amplitude modulation.
Figure 2.6 Superheterodyne (‘superhet’) receiver.
Figure 2.7 Normalised noise power density versus frequency.
Figure 2.8 Thermal noise model using (a) voltage source, and (b) current source.
Figure 2.9 Shot noise.
Figure 2.10 Spectral density of flicker (1/f) noise.
Figure 2.11 Flicker noise translation to high frequency in a nonlinear/linear time-variant system.
Figure 2.12 Spectrum representations for a downconversion mixer.
Figure 2.13 Spectrum showing image band signals at the mixer input and output.
Figure 2.14 Examples of interference in communication systems. (a) Intersymbol interference (ISI). (b) Co-channel interference (CCI). (c) Adjacent channel interference (ACI).
Figure 2.15 Communication channel.
Figure 2.16 Modulation onto different carrier frequencies to allow multiple users to communicate over a single channel.
Figure 2.17 Analogue and digital modulation.
Figure 2.18 Analogue-to-digital conversion.
Figure 2.19 The Shannon limit in a digital communication system.
Figure 2.20 (a) Time-domain waveform of OOK. (b) Symbol diagram of M-ary ASK signals (M = 2, 4 and 8).
Figure 2.21 4-ASK modulation; binary digits, symbols and modulated carrier.
Figure 2.22 BFSK modulation.
Figure 2.23 BPSK modulation.
Figure 2.24 Constellation diagrams of (a) QPSK, (b) QPSK with added white noise, and (c) QPSK with added phase noise.
Figure 2.25 Constellation diagrams of (a) QPSK and (b) 8-PSK.
Figure 2.26 Quadrature modulator and 16- and 64-QAM constellation diagrams.
Figure 2.27 OFDM modulation technique.
Figure 2.28 P_e of modulation techniques versus E_b/N₀ for various values of m.
Figure 2.29 Noise equivalent bandwidth.
Figure 2.30 Noise analysis in series RLC circuit.
Figure 2.31 Input and output signal-to-noise ratios.
Figure 2.32 T_e and NF (T₀ = 290 K).
Figure 2.33 N-stage cascaded subsystem.
Figure 2.34 Selectivity factor.
Figure 2.35 (a) Front-end type I. (b) Front-end type II.
Figure 2.36 Example 60 GHz wireless transmission system.
Figure 2.37 Diagram of wireless link budget calculation.
Figure 2.38 A full-duplex single-conversion superheterodyne transceiver.
Figure 2.39 Simplified single conversion receiver front end.
Figure 2.40 RF filter for image band rejection.
Figure 2.41 A simplified double-conversion receiver.
Figure 2.42 Full-duplex direct-conversion transceiver.
Figure 2.43 LO leakage causing self-mixing.
Figure 2.44 Leakage from the transmitter and self-mixing.
Figure 2.45 Time-varying DC offsets caused by (a) radiated LO or (b) strong interferer.
Figure 2.46 Low-IF receiver.
Figure 2.47 Band-pass sampling receiver.
Figure 2.48 Sampling spectrum from a band-pass sampling receiver.

Chapter 3

Figure 3.1 A two-port network with voltages and currents labelled.
Figure 3.2 Illustration of two networks cascaded, showing the need for a sign change.
Figure 3.3 ABCD matrix of a series impedance or shunt admittance.
Figure 3.4 Interconnected two-port networks.
Figure 3.5 Two-port network represented in terms of voltage waves.
Figure 3.6 Flowgraph representation of a two-port S-parameter network.
Figure 3.7 Simulated S-parameter plot for a simple low-pass filter example.
Figure 3.8 Scattering parameter definition for an N-port linear network.
Figure 3.9 PNA Series Vector Network Analyzer. © 2016, Keysight Technologies, Inc. Reproduced with permission; all rights reserved.
Figure 3.10 Waves in cascaded networks.

Chapter 4

Figure 4.1 Low-pass, high-pass, band-pass and band-stop filters.
Figure 4.2 RC low-pass filter.
Figure 4.3 Example signals in the s-domain.
Figure 4.4 Bode plot for the RC low-pass filter.
Figure 4.5 Achieving a sharper cut off by increasing the order of a Butterworth filter.
Figure 4.6 A pole plotted in quasi-3D to show the pole in a low-pass filter.
Figure 4.7 Ideal low-pass filter response.
Figure 4.8 Impulse response of ideal brick wall low-pass filter.
Figure 4.9 Example receiver constructed from modular components, showing the need for a system impedance.
Figure 4.10 RC filter in a 50 Ω system.
Figure 4.11 Fifth-order Cauer low-pass filter.
Figure 4.12 The prototype filter. (a) Series element first. (b) Shunt element first.
Figure 4.13 Butterworth (or maximally flat) filter response.
Figure 4.14 Poles in the s-domain for a Butterworth filter of order 3 and 4.
Figure 4.15 Chebyshev filter. (a) Frequency response. (b) Pole diagram for n = 5.
Figure 4.16 Elliptical filter response.
Figure 4.17 (a) Low-pass prototype for n = 3. (b) De-normalised values for a cut-off frequency of 100 MHz and 50 Ω impedance.
Figure 4.18 ADS™ circuit schematic and simulated response of the low-pass filter example.
Figure 4.19 Filter behaviour in terms of S-parameters and incident/reflected waves.
Figure 4.20 Low-pass to high-pass transformation on the Bode plot.
Figure 4.21 High-pass filter with n = 5.
Figure 4.22 Low-pass to band-pass transformation.
Figure 4.23 Band-pass filter with n = 3.
Figure 4.24 Low-pass to band-stop transformation.
Figure 4.25 Band-stop filter with n = 3.
Figure 4.26 Summary of filter transformations.
Figure 4.27 Fifth-order band-pass filter.
Figure 4.28 ADS simulation of the fifth-order band-pass filter design example. (a) Magnitude response (S₂₁ and S₁₁). (b) Group delay response.
Figure 4.29 Typical discrete lumped components for RF filters.
Figure 4.30 Simple equivalent circuit models showing parasitic. (a) Resistor. (b) Inductor. (c) Capacitor.
Figure 4.31 Plot of some SMD inductors' impedance versus frequency, showing typical SRF.
Figure 4.32 Plot of some SMD capacitors' impedance versus frequency, showing typical SRF.
Figure 4.33 Capacitively-coupled band-pass filter.
Figure 4.34 Realisation. A K-inverter with a π network.
Figure 4.35 K-inverter-coupled band-pass filter.
Figure 4.36 Narrow-band realisation approach for a K-inverter.
Figure 4.37 Series-shunt capacitive matching network for narrow-band matching.
Figure 4.38 Modified capacitively-coupled resonator filter.

Chapter 5

Figure 5.1 Generic transmission line situation.
Figure 5.2 Coaxial cable. (a) Structure. (b) Cross-section illustrating the electric and magnetic field pattern.
Figure 5.3 Reflection at the end of an open-circuited transmission line.
Figure 5.4 Reflection at the end of a short-circuited transmission line.
Figure 5.5 Simulated current at the short-circuit end of the line for Z_s = 1, 20 and 50 Ω.
Figure 5.6 (a) Twin lead transmission line. (b) Lumped element equivalent circuit of a short section of line.
Figure 5.7 The equivalent circuit of a transmission line using a chain of small sections, each of length Δz.
Figure 5.8 An equivalent circuit model for an infinitesimal transmission line section.
Figure 5.9 Forward (incident) and backward (reflected) waves in a transmission line.
Figure 5.10 Terminated transmission line.
Figure 5.11 Reflections resulting from mismatching at source and load.
Figure 5.12 Standing wave patterns for three different reflection coefficients.
Figure 5.13 Input impedance of a terminated transmission line.
Figure 5.14 The Smith chart.
Figure 5.15 Constant resistance circles.
Figure 5.16 Constant reactance circles.
Figure 5.17 Smith chart formed by combining the constant resistance and constant reactance circles.
Figure 5.18 Admittance chart resulting from rotating the impedance chart by180°.
Figure 5.19 Dual impedance-admittance Smith chart.
Figure 5.20 Constant SWR circles for SWR = 2 and 5.
Figure 5.21 The Keysight Technologies Smith chart tool in ADS.
Figure 5.22 One-port network and its SFG diagram.
Figure 5.23 Signal source and its SFG diagram.
Figure 5.24 Two-port network and its SFG diagram.
Figure 5.25 The SFG diagram for a two-port network with a source connected to port 1 with output impedance Z_s and a load R_L connected to port 2.
Figure 5.26 Middle node removal.
Figure 5.27 Parallel path simplification.
Figure 5.28 Self-loop simplification.
Figure 5.29 Splitting a node.

Chapter 6

Figure 6.1 An assortment of coaxial connector adapters and attenuators (from left to right: APC2.4, APC2.4, SMA, APC7, N-type).
Figure 6.2 Twisted pair line and 300 Ω FM twin-lead ribbon.
Figure 6.3 Rectangular waveguide. (a) Types of waveguide. (b) Rectangular waveguide structure.
Figure 6.4 TE₁₀ and TE₂₀ propagation modes in a rectangular waveguide (E-field).
Figure 6.5 (a) Microstrip transmission line, with the key parameters labelled. (b) Approximate E- and H-field patterns in cross-section.
Figure 6.7 Examples of microstrip components in ADS™.
Figure 6.8 A typical coax-microstrip launcher cross-section.
Figure 6.9 Microstrip ribbon inductor. (a) Layout. (b) Equivalent circuit.
Figure 6.10 Microstrip spiral inductor and interdigital capacitor.
Figure 6.11 Input admittance of an open-circuited parallel stub versus electrical length.
Figure 6.12 Field effect transistor (FET) biasing using a short-circuited parallel stub.
Figure 6.13 Radial and butterfly stubs.
Figure 6.14 (a) Microstrip layout of the Wilkinson power splitter. (b) Multisection broadband circuit schematic.
Figure 6.15 Symmetrical parallel-coupled microstrip lines, indicating key design parameters and the port definitions.
Figure 6.16 Approximate field patterns for even and odd mode in parallel-coupled microstrip.
Figure 6.17 Layout of a four-finger Lange coupler.
Figure 6.18 Microstrip branch-line coupler.
Figure 6.19 Microstrip rat-race coupler.
Figure 6.20 Planar Marchand balun and GaAs spiral coupler realisation.
Figure 6.21 Common forms of microstrip resonator. (a) Half-wavelength resonator. (b) Quarter-wavelength resonator. (c) Ring resonator. (d) Disc resonator. (e) Dielectric puck.
Figure 6.22 Coplanar waveguide structure.
Figure 6.23 (a) Coplanar strip transmission line (CPS). (b) Slotline.
Figure 6.24 (a) Stripline. (b) Suspended stripline. (c) Suspended microstrip. (d) Inverted microstrip.
Figure 6.25 Thin-film microstrip transmission line medium.
Figure 6.26 Schematic diagrams of (a) a lumped-distributed branch-line coupler, and (b) a rat race coupler.
Figure 6.27 Substrate integrated waveguide. (a) SIWs in PCB technology, with transitions to microstrip. (b) Detail of the waveguide structure.
Figure 6.28 Cross-section of (a) ridged waveguide, (b) an E-plane circuit using an all-metal insert and (b) finline.
Figure 6.29 Cross-section of (a) dielectric image guide, (b) dielectric insular image guide, (c) nonradiative dielectric guide (NRD), and (d) rib image guide.
Figure 6.30 (a) Micromachined suspended microstrip. (b) Micromachined rectangular waveguide.

Chapter 7

Figure 7.1 Lumped elements converted to shunt stubs.
Figure 7.2 A series lines used as a series inductor.
Figure 7.3 Input impedance and admittance of terminated K- and J-inverters.
Figure 7.4 (a) K-inverter terminated with and inductor, and (b) J-inverter terminated with a capacitor.
Figure 7.5 Equivalent networks using (a) K-inverter and (b) J-inverter.
Figure 7.6 Converting a low-pass filter to a purely-capacitive topology using J-inverters.
Figure 7.7 Converting a band-pass filter prototype to a J-inverter based band-pass filter.
Figure 7.8 Generalised band-pass filters based on (a) K- and (b) J-inverters.
Figure 7.9 Lumped element inverters.
Figure 7.10 (a) J-inverter band-pass filter. (b) Lumped-inverter based band-pass filter. (c) Capacitive coupling band-pass filter.
Figure 7.11 Lumped-distributed topologies for K-inverter realisation using (a) a negative, and (b) a positive length of transmission line.
Figure 7.12 Lumped-distributed topologies for J-inverter realisation using (a) negative- and (b) positive-length transmission line.
Figure 7.13 Lumped-distributed implementations for (a) K-inverter using T-network and (b) J-inverter using Π-network.
Figure 7.14 J-inverter realisation with distributed Π-network.
Figure 7.15 Schematics of (a) lumped element low-pass filter at 1 GHz, and (b) transmission line counterpart.
Figure 7.16 Kuroda's identities.
Figure 7.17 Transmission matrix definitions of (a) shunt stubs and (b) series stubs.
Figure 7.18 (a) A low-pass filter, and (b) its modified topology by adding lines at the input and output ports.
Figure 7.19 Filter design obtained by applying Kuroda's identities to the filter in Figure 7.18(b).
Figure 7.20 Coupled-lines section as a filter element.
Figure 7.21 Stepped-impedance topologies and lumped-element prototypes.
Figure 7.22 Final designs for the stepped-impedance low-pass filter.
Figure 7.23 Parallel-coupled line filter with open-circuit resonators.
Figure 7.24 Open-ended coupled-line section and its equivalent circuit.
Figure 7.25 Circuit model for a cascaded coupled-lines filter based on J-inverters and UEs.
Figure 7.26 Half-wavelength UE as a parallel resonator.
Figure 7.27 J-inverter band-pass model for the parallel-coupled band-pass filter.
Figure 7.28 Coupled-line band-pass filter.
Figure 7.30 Interdigital filter network.
Figure 7.31 Circuit model for an interdigital filter using (a) short-circuited coupled lines, and (b) quarter-wave transmission lines and short-circuited stubs.
Figure 7.32 Circuit model for an interdigital band-pass filter using J-inverters and short-circuited stubs.
Figure 7.33 (a) Self and coupling capacitance modelled for an interdigital filter. (b) Two self-capacitances resulting from splitting a single conductor.
Figure 7.34 Asymmetrical coupled-line model for a five-conductor interdigital filter.
Figure 7.35 Final design for the fifth order interdigital filter.
Figure 7.36 Combline filter network.
Figure 7.37 Coupled-line model for a combline filter.
Figure 7.38 Equivalent circuit model for a combline filter using shunt and series stubs.
Figure 7.39 Equivalent circuit for (a) J-inverter using a series stub and (b) series stub using a J-inverter.
Figure 7.40 Equivalent circuit for input and output matching networks of a combline filter.
Figure 7.41 A model for a combline filter obtained by replacing input/output network and shorted series stubs with the networks in Figures 7.39 and 7.40.
Figure 7.42 Model for designing a combline filter.
Figure 7.43 (a) Tapped-line and (b) coupled-line matched hairpin filters.
Figure 7.44 Equivalent circuit for a tapped U-shaped resonator.
Figure 7.45 Comparison of the frequency responses of seventh-order elliptic and Chebyshev filters with the same degree of pass-band ripple.
Figure 7.47 General cross-coupled filter.

Chapter 8

Figure 8.2 Photolithographic patterning of a conductor layer.
Figure 8.3 Cross-section of NMOS device and photographic image of an interconnect stack. Source: Brain, R. et al. (2009) Reproduced with permission of IEEE.
Figure 8.5 Feature size reduction versus Year.
Figure 8.6 Diffraction effect in photolithography.
Figure 8.7 Diagrammatic representation of the More than Moore paradigm.
Figure 8.8 Simplified representations comparing ‘top-down’ (left) and ‘bottom-up’ nanofabrication (right).
Figure 8.9 Cross-section of a typical GaAs pHEMT.
Figure 8.10 Typical low-noise pHEMT I–V curves.
Figure 8.11 HEMT small-signal equivalent circuit.
Figure 8.12 Left: 2 × 150 HEMT. Right: 4 × 75 HEMT.
Figure 8.13 The effect of HEMT geometry on maximum stable/available gain versus frequency.
Figure 8.14 Layout of a typical MOSFET for increased high-frequency power output with low gate resistance.
Figure 8.15 Basic n-p-n transistor.
Figure 8.16 Basic n-p-n transistor in cross-section.
Figure 8.17 High-frequency, small-signal π-model for a bipolar transistor.
Figure 8.18 HBT band diagram.
Figure 8.19 InGaP/GaAs HBT cross-section.
Figure 8.20 (a) A bare chip FET assembled into a microstrip circuit. (b) Typical parasitics of a bare-chip device when in a circuit.
Figure 8.21 Typical ceramic packages for a low-noise device (left) and power device (right).
Figure 8.22 Smith chart plot of S₁₁ for a bare-chip FET, compared with a packaged FET.
Figure 8.23 FET I–V curves with Class A resistive load line.
Figure 8.24 Packaged power device. Single-layer capacitors are integrated inside the package and combine with the bond-wire inductances to ease matching.
Figure 8.25 GaAs MMIC 60 GHz balanced three-stage amplifier.
Figure 8.26 RFIC receiver. Source: Wickert, M. et al. (2012) Reproduced with permission of IEEE.
Figure 8.27 Spiral inductors. (a) Standard spiral with an underpass. (b) Single-ended stacked spiral. (c) Interwound windings.
Figure 8.28 Inductor model.
Figure 8.29 Schottky diode. (a) Bare chip air bridge mesa diode. (b) Beam-lead device.

Chapter 9

Figure 9.1 Amplifier chain illustrating the need for a system impedance.
Figure 9.2 Basic source and load circuit.
Figure 9.3 Graph of load power versus load resistance.
Figure 9.4 Source connected to load through a transmission line.
Figure 9.5 Smith chart representations for connecting a circuit with (a) a series inductor, (b) a series capacitor, (c) a parallel capacitor, and (d) a parallel inductor.
Figure 9.6 L-network for two conditions. (a) R_L < Z₀. (b) G_L < 1/Z₀.
Figure 9.7 L-network circuit topologies for R_L < Z₀, showing the regions of applicability for Z_L on the Smith chart (each network can be used only for Z_L in the respective shaded area).
Figure 9.8 L-network circuit topologies for G_L < 1/Z₀, showing the regions of applicability for Z_L on the Smith chart (each network can be used only in the respective shaded area).
Figure 9.9 C-L-C π-network for impedance matching.
Figure 9.10 L-C-L T-network circuit diagram.
Figure 9.11 Stub matching with a shunt or series stub.
Figure 9.12 Single stub matching.
Figure 9.13 Stub matching example on the Smith chart.
Figure 9.14 Quarter-wave transmission line matching.
Figure 9.15 Frequency response with single-section quarter-wave transformer.
Figure 9.16 Multisection quarter-wave transformer.
Figure 9.17 Multisection quarter-wave transformer frequency response.
Figure 9.18 Illustration of change in electrical length with signal frequency.
Figure 9.19 S₁₁ plot showing cyclical behaviour of the matching network.

Chapter 10

Figure 10.1 Intrinsic FET linear model.
Figure 10.2 FET configurations. (a) Common source. (b) Common gate. (c) Cascode.
Figure 10.3 HBT configurations. (a) Common emitter. (b) Common base. (c) Common collector. (d) Cascode.
Figure 10.4 Illustration of positive feedback in a public address system.
Figure 10.5 Flowgraph representation of a transistor with a load on its output.
Figure 10.6 Stability circles on the Smith chart. The two most common situations.
Figure 10.7 Idealised maximum gain response of a transistor.
Figure 10.8 Example of gain and stability circles (K < 1).
Figure 10.9 Basic bias circuits. (a) Bias chokes. (b) Short-circuit stubs. (c) An active load.
Figure 10.10 A generic two-stage reactively matched amplifier.
Figure 10.11 (a) FET feedback amplifier. (b) Darlington pair broadband amplifier. (c) Long-tailed pair.
Figure 10.12 A four-section distributed amplifier using FETs.
Figure 10.13 Balanced amplifier configuration.
Figure 10.14 Noise figure of an LNA in terms of the display on a spectrum analyser.
Figure 10.15 Example noise circles on the Smith chart.
Figure 10.16 Input-output power characteristic illustrating the 1-dB gain compression point.
Figure 10.17 Frequency spectrum illustrating second-order intermodulation products.
Figure 10.18 Graphical representation of second-order intercept point with fundamental and intermodulation signals.
Figure 10.19 Frequency spectrum of illustrating third-order intermodulation products.
Figure 10.20 Graphical representation of third-order intercept point with fundamental and intermodulation signals.
Figure 10.21 Nonlinear distortion of IQ-modulated signals. (a) Spectral regrowth. (b) Error vector magnitude (EVM).
Figure 10.22 Generic I–V curves for a transistor.
Figure 10.23 Class A common-emitter BJT amplifier.
Figure 10.24 Waveform of the collector current of the Class A amplifier.
Figure 10.25 Class B narrowband amplifier circuit diagram.
Figure 10.26 Current waveform in the class B amplifier.
Figure 10.27 Class B push-pull topology. (a) Circuit diagram. (b) Waveform showing cross-over distortion.
Figure 10.28 Current waveform of a class AB amplifier.
Figure 10.29 Class C amplifier waveform.
Figure 10.30 Block diagram of class D amplifier.
Figure 10.31 Class D amplifier PWM waveform.
Figure 10.32 Class E amplifier configuration.
Figure 10.33 Class F amplifier.
Figure 10.34 Power amplifier using corporate or binary power splitting/combining.
Figure 10.35 Power combining using the balanced amplifier technique.
Figure 10.36 Simplified illustration of the enhanced cluster matching technique.
Figure 10.38 Spatial power-combining principle.
Figure 10.39 Feedback system.
Figure 10.40 Feedforward linearisation block diagram.

Chapter 11

Figure 11.1 (a) A one-port negative-resistance oscillator model. (b) Characteristic function of a nonlinear resistor.
Figure 11.2 A simplified one-port linear circuit model for an oscillator.
Figure 11.3 Clapp oscillator schematic circuit diagram and small-signal model.
Figure 11.4 Two-port oscillator model: positive feedback.
Figure 11.5 Oscillation mechanism periods, from (a) initial, (b) amplified, (c) feedback, and (d) the stable state.
Figure 11.6 Oscillator based on a shunt-shunt feedback topology of (a) π and (b) T.
Figure 11.7 Colpitts oscillator. (a) AC circuit. (b) Small-signal feedback model.
Figure 11.8 Conjugate poles and the unit step responses for (a) σ < 0, (b) σ = 0 (critically damped), and c) σ > 0.
Figure 11.9 Mapping from a Nyquist contour on the s-plane through a function F(s) to produce a Nyquist diagram.
Figure 11.10 From s-plane to Nyquist contour. (a) Pole positions. (b) Nyquist contour.
Figure 11.11 Nyquist contour and Nyquist diagram of loop gain
Figure 11.12 Timing jitter.
Figure 11.13 Effect of timing jitter in an analogue-to-digital converter.
Figure 11.14 The importance of phase noise in multichannel communication. A receiver with (a) an ideal local oscillator and (b) an oscillator with phase noise.
Figure 11.15 Generic noise spectrum for an oscillator.
Figure 11.16 Characteristics of (a) short-circuited and (b) open-circuited transmission lines.
Figure 11.17 Quartz crystal, AT and BT cuts, and equivalent circuits.
Figure 11.18 Schematic of (a) Colpitts oscillator, and (b) its AC small-signal model.
Figure 11.19 Colpitts oscillator. (a) Simplified AC model. (b) Equivalent circuit for calculating Z_r(ω).
Figure 11.20 Common-emitter Colpitts oscillator. (a) Circuit schematic. (b) AC model.
Figure 11.21 Circuit model for computing driving-point impedance seen from the RL subnetwork.
Figure 11.22 Schematic of (a) the tuned amplifier, and (b) its AC small-signal model.
Figure 11.23 Cross-coupled oscillator formed from two tuned amplifiers. (a) Conceptual diagram. (b) Schematic circuit diagram.
Figure 11.24 Cross-coupled oscillator circuit with (a) emitter-to-ground and (b) current source-to-ground.
Figure 11.25 Applying the one-port oscillator model (negative resistance technique) to the cross-coupled oscillator.
Figure 11.26 MOS varactor symbol and device cross-section.
Figure 11.27 Conceptual diagram of a VCO.
Figure 11.28 Phase-locked loop block diagram.
Figure 11.29 Spectrum of (a) free-running VCO with random white phase noise, and (b) PLL output.
Figure 11.30 Phase recovery PLL.
Figure 11.31 An integer-N PLL-based frequency synthesiser.
Figure 11.32 Flowchart for oscillator design.
Figure 11.33 Nonlinear oscillator design and layout optimisation.
Figure 11.34 Oscillator design description with scattering parameters.
Figure 11.35 Feedback techniques applied to destabilise a transistor.
Figure 11.36 Output stability circle of the transistor in the example.
Figure 11.37 Final design from the example.

Chapter 12

Figure 12.1 Sum and difference frequency outputs from ideal multiplication of RF and LO.
Figure 12.2 (a) Mixing using the nonlinear I–V characteristic of a device. (b) Conceptual single-ended mixer using a diode.
Figure 12.3 Output spectrum of a downconversion mixer with the LO signal power assumed to be significantly larger than the RF.
Figure 12.4 Mixer as a switch driven by the LO.
Figure 12.5 Schottky diode model.
Figure 12.6 (a) FET I–V curves showing mixing modes. (b) A dual-gate FET mixer.
Figure 12.7 (a) Single-ended resistive FET mixer. (b) Operation on I–V curves.
Figure 12.8 Single-balanced diode mixers. (a) Using a 180° hybrid. (b) Using a 90° coupler.
Figure 12.9 Double-balanced mixer representation with four commutating switch elements.
Figure 12.10 Double-balanced dual-gate FET mixer.
Figure 12.11 Image-rejection architectures. (a) Hartley. (b) Weaver.
Figure 12.13 Planar Marchand balun.
Figure 12.14 Lumped-element 90° splitter.
Figure 12.15 Examples of active balun circuits. (a) Differential pair. (b) Common-source/common-gate pair.
Figure 12.16 Double-balanced diode ring mixer.
Figure 12.17 Gilbert cell mixer.
Figure 12.19 (a) Dual-Gate FET distributed mixer. (b) A GaAs MMIC distributed mixer.
Figure 12.20 A generic millimetre-wave single-balanced diode mixer.
Figure 12.21 (a) I-Q constellation for 16-QAM. (b) I-Q Vector modulator using mixers.
Figure 12.22 (a) Circuit topology of the bi-phase amplitude modulator. (b) Typical GaAs HEMT S₁₁ versus bias voltage, at 60 GHz.

Chapter 13

Figure 13.1 A block diagram of an RF MEMS reconfigurable transceiver. (a) Transmitter module. (b) Superheterodyne-based receiver.
Figure 13.2 A micromachined on-chip recta-coax line [5]. Source: Reid, J.R. et al. (2006). Reproduced with permission of IEEE.
Figure 13.3 Scanning electron microscopy images of robust inductor [7]. Source: Jr-Wei Lin, Chen et al. (2005). Reproduced with permission of IEEE.
Figure 13.4 MEMS tuneable capacitor based on in-phase moveable sidewalls of the ground layer.
Figure 13.5 Switches developed at (a) Hughes Research Laboratories and (b) Rockwell Science Centre [11]. Source: Brown, E.R. (1998). Reproduced with permission of IEEE.
Figure 13.6 Switch developed at Texas Instruments [11]. Source: Brown, E.R. (1998). Reproduced with permission of IEEE.
Figure 13.7 Circuit diagram of an eight-element reconfigurable matching network [12].
Figure 13.8 An example of a digital MEMS phase shifter and its phase response.
Figure 13.9 Photograph of a UHF five-pole MEMS reconfigurable filter [19]. Source: Brank, J. et al. (2001). Reproduced with permission of IEEE.
Figure 13.10 Reconfigurable rectangular spiral antenna [22]. Source: Haridas, N. et al. (2008). Reproduced with permission of IEEE.
Figure 13.11 Micromachined patch antenna integrated with MEMS varactors [23]. Source: Erdil, E. et al. (2007). Reproduced with permission of IEEE.
Figure 13.12 Surface micromachining technique.
Figure 13.13 Zero-level packaging process flow.

Chapter 14

Figure 14.1 Dipole antenna.
Figure 14.2 Radiation pattern of a short dipole antenna.
Figure 14.3 Current distribution of a half-wave dipole antenna.
Figure 14.4 Folded dipole antenna.
Figure 14.5 Monopole antenna.
Figure 14.6 Loop antenna.
Figure 14.7 Yagi–Uda antenna.
Figure 14.8 Parabolic antenna.
Figure 14.9 Pyramidal waveguide horn antenna and its radiation pattern.
Figure 14.10 Microstrip patch antenna.
Figure 14.11 Transmission system parameters for Friis' transmission equation.
Figure 14.12 Ericsson in-building path loss model.
Figure 14.13 (a) Three-element array. (b) Calculated radiation pattern of the array.
Figure 14.14 Basic MIMO system.

Chapter 15

Figure 15.1 Effect of imbalance in the quadrature modulator for (a) zero-IF, and (b) low-IF transmitters.
Figure 15.2 Effect of I and Q mismatch to the IRR performance of image rejection receiver.
Figure 15.3 2 × 2 MIMO transceiver.
Figure 15.4 Analogue-to-digital conversion.
Figure 15.5 A 1 MHz sinusoidal waveform which is sampled at (a) 4 MHz and (b) 1.5 MHz.
Figure 15.6 Time- and frequency-domains of waveforms which is sampled and the sampled signal: (a) x(t); (b) δ(t); (c) x_s(t); (d) X(f); (e) δ(f); (f) X_s(f).
Figure 15.7 Uniform and nonuniform quantisation.
Figure 15.8 Decomposing a time-domain signal of eight data points.
Figure 15.9 Decomposition step which is equivalent to a bit reversion process.
Figure 15.10 Basic FFT cell; a butterfly diagram.
Figure 15.11 FFT applied to compute an eight-point spectrum.
Figure 15.12 Vector P₀ rotates to P with θ.
Figure 15.13 Convergence of K versus N.
Figure 15.14 (a) Ideal I–Q modulator transmitter. (b) I–Q imbalance model.
Figure 15.15 Practical implementation forms of (a) an I–Q demodulator, and (b) with imbalance effect.
Figure 15.16 Loop back receiver applied to direct conversion transmitter.
Figure 15.17 Baseband digital predistortion technique.
Figure 15.18 LUT implementation for PD function.
Figure 15.19 Direct adaptation topology.
Figure 15.20 Comparison of the number of occupied channels for FDM and OFDM.
Figure 15.21 Multiple sinc spectrum components in the OFDM technique.
Figure 15.22 Mathematical model for OFDM.
Figure 15.23 Simplified diagram of a MIMO receiver.

Chapter 16

Figure 16.1 Simplified (a) transmitter and (b) receiver block diagrams.
Figure 16.2 Conceptual partitioning of active and passive components for a transceiver module.
Figure 16.3 Cross-section of a typical multilayer PCB.
Figure 16.4 Multilayer laminate PCB (8 × 8^″) containing a number of microwave circuits, prior to mounting of components.
Figure 16.5 A thin-film circuit using a gold conductor on an alumina substrate, mounted in a test fixture with SMA launchers.
Figure 16.6 Screen printing of solder paste using a mesh (or screen).
Figure 16.7 The photoimageable thick-film process.
Figure 16.8 Examples of microwave components fabricated with photoimageable thick-film technology. From left to right: spiral inductor; SIW; chip cavity using photoimageable dielectric.
Figure 16.9 Diagrammatic representation of the main LTCC processing steps.
Figure 16.10 Chip-on-board assembly.
Figure 16.11 Lead frame package.
Figure 16.12 (a) Microwave MMIC in a plastic over-moulded QFN package. (b) Microwave MMIC mounted on a laminate PCB. Illustration courtesy of Plextek RFI, used with permission. All rights reserved.
Figure 16.13 Cross-section through a typical ball-grid array (BGA) package.
Figure 16.14 Flip-chip assembly.
Figure 16.15 3-D integration of a millimetre-wave module using TSVs and stacked RFICs.
Figure 16.16 Components supplied in tape-and-reel form for automated assembly.
Figure 16.17 A conceptual system-in-package using a multilayer substrate.
Figure 16.18 Conceptual system-on-substrate multi-band transceiver.
Figure 16.19 Microwave components printed onto acetate sheet with carbon-based ink.
Figure 16.20 Examples of transitions and antenna integration techniques.
Figure 16.21 Conceptual terahertz system-on-substrate using III–V ICs on a Si/SiGe RFIC motherboard.

Chapter 17

Figure 17.1 MMIC simulation in ADS™.
Figure 17.2 Microstrip Wilkinson power divider schematic in ADS™.
Figure 17.3 First-order nonlinear circuit.
Figure 17.4 Voltage waveform derived from the Euler method.
Figure 17.5 The concept of partitioning a network into linear and nonlinear subnetworks.
Figure 17.6 Equivalent circuit of single-ended diode mixer.
Figure 17.7 Small-signal model of single-ended diode mixer for conversion matrix analysis.
Figure 17.8 Via hole meshing.
Figure 17.9 Square plate with 25 mesh elements.
Figure 17.10 Part of a typical test mask for PDK development.

Chapter 18

Figure 18.1 Keysight DSOX3000 series digital oscilloscope. © 2016 Keysight Technologies, Inc. Reproduced with permission.
Figure 18.2 Example screenshot of the Keysight VSA software. © 2016 Keysight Technologies, Inc. Reproduced with permission.
Figure 18.3 Keysight 33220A function/arbitrary waveform generator. © 2016 Keysight Technologies, Inc. Reproduced with permission.
Figure 18.4 Keysight precision LCR meter with test fixture for surface-mount devices. © 2016 Keysight Technologies, Inc. Reproduced with permission.
Figure 18.5 Keysight N9310A 9 kHz to 3 GHz signal generator. © 2016 Keysight Technologies, Inc. Reproduced with permission.
Figure 18.6 Swept frequency spectrum analyser block diagram.
Figure 18.7 (a) Oscilloscope (time-domain) measurement. (b) Spectrum analyser (frequency domain) measurement of a sine wave signal.
Figure 18.9 Simplified block diagram of a vector signal analyser with digital IF.
Figure 18.10 Voltage standing wave ratio (VSWR) and impedance measurement with a slotted line.
Figure 18.12 Simplified block diagram of a VNA with S-parameter test set.
Figure 18.13 (a) Typical VNA measurement of a two-port DUT, using cables. (b) Example of measurement ripple (through line measurement).
Figure 18.14 Errors in the one-port measurement system.
Figure 18.15 One-port error model flowgraph.
Figure 18.16 12-term error model (forward path) for two-port measurements.
Figure 18.17 A mechanical calibration kit in a box. The kit contains calibration standards, adapters, spanners and gauges. © 2016 Keysight Technologies, Inc. Reproduced with permission.
Figure 18.18 Determining the directivity term using a sliding load.
Figure 18.19 Simplified block diagram of a typical electronic calibration module.
Figure 18.20 VNA screenshots before calibration. (a) S₂₁ (0.5 dB per division) and S₁₁ (10 dB per division) for a thru line (the reference line is 0 dB). (b) S₁₁ of the offset short circuit standard on the Smith chart display.
Figure 18.21 VNA screenshots after calibration. (a) S₂₁ and S₁₁ for the thru line. (b) S₁₁ of the offset short circuit standard on the Smith chart display.
Figure 18.22 APC3.5 mm connector: This is the male end (or plug). © 2016 Keysight Technologies, Inc. Reproduced with permission.
Figure 18.23 Time-domain measurement example.
Figure 18.24 A typical two-port test fixture.
Figure 18.25 TRL in-fixture calibration example.
Figure 18.26 (a) Cascade Microtech® 110 GHz probes. (b) Coplanar waveguide (CPW) tips.
Figure 18.27 RF-on-wafer (RFOW) measurement of a capacitor.
Figure 18.28 (a) Microstrip, single-ended. (b) Differential CPS line. (c) CPS with ground plane.
Figure 18.29 Mixed-mode S-parameter matrix.
Figure 18.30 (a) Cross-section of a typical slabline tuner. (b) An early prototype of an automated tuner developed at the University of Leeds [12].
Figure 18.31 X-parameter representation of a nonlinear device.